Staff ASIC Design Engineer

Description du poste

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise.

Join the Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.

Qualifications

• B.Sc. in Elec / Computer Engineering is a must, higher degrees preferred
• Minimum of 5+ years ASIC design experience
• Solid design (micro-architecture / implementation) and debugging skills
• Working knowledge of DSP / FEC and communication theories
• Strong problem-solving skills
• Good verbal / written communication skills and teamwork
• Good knowledge of ASIC design flow / tools, with backend knowledge being a great asset
• Working knowledge of MatLab and other scripting languages
• Knowledge of OTN, CAUI and other telecom protocols
• Design Experience with ethernet standards 100G to 800G would be an asset:
• 100GE – cl45, cl49, CL82, CL91, CL119
• 200Ge, 400Ge – cl161, cl116
• 800ge – 802.df / 800ETA
• PTP 1588 Standard
• Ethernet frame types
• Packet insertion / extraction

Responsibilities

• Working as an independent contributor in development and verification of the world-leading SoCs based on latest technology ASICs and FPGAs
• Working as an independent contributor in algorithm development, fixed-point modelling and fixed-point performance verification
• Working with experts of different areas to ensure the most competitive solutions
• Cooperating with system engineers, HW / SW development, suppliers and other relevant functions to solve technical issues
• Supporting HW / SW bring-up and debug

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