FPGA Designer / Verification Engineer

Company Description

Accedian Networks is the leader in Performance Assured Networking™ for mobile backhaul, business ethernet services and cloud connectivity. Our solutions provide service providers and network operators visibility into their networks and this differentiating ability empowers them to optimize, improve and manage the performance of their network.

Job Description

This position is for an FPGA Designer / Verification Engineer. It reports to the Manager of FPGA development. We are looking for an FPGA Design / Verification Engineer that can potentially contribute to all phases of FPGA development with specific emphasis on verification. This position requires a strong understanding in FPGA development from concept to an implemented and verified design.

Responsibilities :

• Full FPGA development cycle involving architecture definition, verification strategy definition, RTL / Testbench coding, simulation, timing analysis, synthesis, place & route and on-board testing.
• Validate that system meets design requirement : Write test plans for RTL validation. Develop verification collateral (such as BFMs, behavioral checkers, coverage monitors, or score-boards). Define and run system simulation models, and find and implement corrective measures for failing RTL tests. Analyze and use results to modify testing.
• Build and maintains tools and processes associated with FPGA development.
• Participate in project planning activities.
• Understand product requirements, participate in software / FPGA partitioning and implement / validate FPGA functional blocks.
• Work with other engineers on a team to integrate FPGA designs on projects that include hardware and software design components

Qualifications

Additional Information

All your information will be kept confidential according to EEO guidelines.